 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| kinetis kl27 microcontroller 48 mhz arm? cortex?-m0+ and 128/256 kb flash the kl27 series is optimized for cost-sensitive and battery- powered applications requiring low-power usb connectivity. the product offers: ? usb fs 2.0 device without requiring an external crystal ? embedded rom with boot loader for flexible program upgrade ? high accuracy internal voltage and clock reference ? flexio to support any standard and customized serial peripheral emulation ? down to 54ua/mhz in very low power run mode and 1.96ua in deep sleep mode (ram + rtc retained) core processor ? arm ? cortex ? -m0+ core up to 48 mhz memories ? 128/256 kb program flash memory ? 32 kb sram ? 16 kb rom with build-in bootloader ? 32-byte backup register system ? 4-channel asynchronous dma controller ? watchdog ? low-leakage wakeup unit ? two-pin serial wire debug (swd) programming and debug interface ? micro trace buffer ? bit manipulation engine ? interrupt controller clocks ? 48mhz high accuracy (up to 0.5%) internal reference clock ? 8mhz/2mhz high accuracy (up to 3%) internal reference clock ? 1khz reference clock active under all low-power modes (except vlls0) ? 32C40khz and 3C32mhz crystal oscillator peripherals ? usb full-speed 2.0 device controller supporting crystal-less operation ? one uart module supporting iso7816, operating up to 1.5 mbit/s ? two low-power uart modules supporting asynchronous operation in low-power modes ? two i2c modules and i2c0 supporting up to 1 mbit/s ? two 16-bit spi modules supporting up to 24 mbit/s ? one flexio module supporting emulation of additional uart, irda, spi, i2c, i2s, pwm and other serial modules, etc. ? one serial audio interface i2s ? one 16-bit 818 ksps adc module with high accuracy internal voltage reference (vref) and up to 16 channels ? high-speed analog comparator containing a 6-bit dac for programmable reference input ? one 12-bit dac ? 1.2 v internal voltage reference timers ? one 6-channel timer/pwm module ? two 2-channel timer/pwm modules ? one low-power timer ? periodic interrupt timer ? real time clock mkl27z128vxx4 mkl27z256vxx4 32 qfn 5x5 mm p 0.5 mm 48 qfn 7x7 mm p 0.5 mm 64 lqfp 10x10 mm p 0.5 mm 64 bga 5x5 mm p 0.5 mm freescale semiconductor, inc. KL27P64M48SF6 data sheet: technical data rev. 5, 08/2015 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012C2015 freescale semiconductor, inc. all rights reserved.
operating characteristics ? voltage range: 1.71 to 3.6 v ? flash write voltage range: 1.71 to 3.6 v ? temperature range: C40 to 105 c packages ? 64 lqfp 10mm x 10mm, 0.5mm pitch, 1.6mm thickness ? 64 mapbga 5mm x 5mm, 0.5mm pitch, 1.23mm thickness ? 48 qfn 7mm x 7mm, 0.5mm pitch, 0.65mm thickness ? 32 qfn 5mm x 5mm, 0.5mm pitch, 0.65mm thickness security and integrity ? 80-bit unique identification number per chip ? advanced flash security i/o ? up to 50 general-purpose input/output pins (gpio) and 6 high-drive pad low power ? down to 54ua/mhz in very low power run mode ? down to 1.96ua in vlls3 mode (ram + rtc retained) ? six flexible static modes ordering information product memory package io and adc channel part number marking (line1/ line2) flash (kb) sram (kb) pin count package gpios gpios (int/hd) 1 adc channels (se/dp) mkl27z128vfm4 m27p7v 128 32 32 qfn 23 19/6 7/0 mkl27z256vfm4 m27p8v 256 32 32 qfn 23 19/6 7/0 mkl27z128vft4 m27p7v 128 32 48 qfn 36 24/6 14/1 mkl27z256vft4 m27p8v 256 32 48 qfn 36 24/6 14/1 mkl27z128vlh4 mkl27z128v//lh4 128 32 64 lqfp 50 31/6 16/2 mkl27z256vlh4 mkl27z256v//lh4 256 32 64 lqfp 50 31/6 16/2 mkl27z128vmp4 m27p7v 128 32 64 mapbga 50 31/6 16/2 mkl27z256vmp4 m27p8v 256 32 64 mapbga 50 31/6 16/2 1. int: interrupt pin numbers; hd: high drive pin numbers related resources type description resource selector guide the freescale solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. kl2xpb 1 reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. KL27P64M48SF6rm 1 data sheet the data sheet includes electrical characteristics and signal connections. this document. chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_l_1n71k 1 package drawing package dimensions are provided in package drawings. 64-lqfp: 98ass23234w 1 64 mapbga: 98asa00420d 1 32 qfn: 98asa00615d 1 48 qfn: 98asa00616d 1 1. to find the associated resource, go to http://www.freescale.com and perform a search using this term. 2 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. kinetis kl27 microcontroller, rev.5, 08/2015. 3 freescale semiconductor, inc. table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 5 2 general................................................................................... 6 2.1 ac electrical characteristics.............................................6 2.2 nonswitching electrical specifications..............................7 2.2.1 voltage and current operating requirements....... 7 2.2.2 lvd and por operating requirements................7 2.2.3 voltage and current operating behaviors.............8 2.2.4 power mode transition operating behaviors........ 9 2.2.5 power consumption operating behaviors............ 10 2.2.6 emc radiated emissions operating behaviors..... 20 2.2.7 designing with radiated emissions in mind..........21 2.2.8 capacitance attributes.........................................21 2.3 switching specifications...................................................21 2.3.1 device clock specifications..................................21 2.3.2 general switching specifications......................... 22 2.4 thermal specifications..................................................... 22 2.4.1 thermal operating requirements......................... 22 2.4.2 thermal attributes................................................23 3 peripheral operating requirements and behaviors.................. 24 3.1 core modules.................................................................. 24 3.1.1 swd electricals .................................................. 24 3.2 system modules.............................................................. 25 3.3 clock modules................................................................. 25 3.3.1 mcg-lite specifications.......................................25 3.3.2 oscillator electrical specifications........................27 3.4 memories and memory interfaces................................... 29 3.4.1 flash electrical specifications.............................. 29 3.5 security and integrity modules........................................ 31 3.6 analog............................................................................. 31 3.6.1 adc electrical specifications............................... 31 3.6.2 voltage reference electrical specifications.......... 36 3.6.3 cmp and 6-bit dac electrical specifications....... 37 3.6.4 12-bit dac electrical characteristics....................39 3.7 timers..............................................................................42 3.8 communication interfaces............................................... 42 3.8.1 usb electrical specifications............................... 42 3.8.2 usb vreg electrical specifications.................... 43 3.8.3 spi switching specifications................................ 43 3.8.4 i2c....................................................................... 48 3.8.5 uart...................................................................50 3.8.6 i2s/sai switching specifications.......................... 50 4 dimensions............................................................................. 54 4.1 obtaining package dimensions....................................... 54 5 pinouts and packaging........................................................... 55 5.1 kl27 signal multiplexing and pin assignments...............55 5.2 kl27 family pinouts........................................................57 6 ordering parts......................................................................... 61 6.1 determining valid orderable parts....................................61 7 part identification.....................................................................61 7.1 description.......................................................................61 7.2 format............................................................................. 62 7.3 fields............................................................................... 62 7.4 example...........................................................................62 8 terminology and guidelines.................................................... 63 8.1 definitions........................................................................ 63 8.2 examples......................................................................... 63 8.3 typical-value conditions.................................................. 64 8.4 relationship between ratings and operating requirements....................................................................64 8.5 guidelines for ratings and operating requirements..........65 9 revision history...................................................................... 65 4 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 1 ratings 1.1 thermal handling ratings table 1. thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life. 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 1.2 moisture handling ratings table 2. moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 1.3 esd handling ratings table 3. esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model C2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model C500 +500 v 2 i lat latch-up current at ambient temperature of 105 c C100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm). 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components. 3. determined according to jedec standard jesd78, ic latch-up test. ratings kinetis kl27 microcontroller, rev.5, 08/2015. 5 freescale semiconductor, inc. 1.4 voltage and current operating ratings table 4. voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 120 ma v io io pin input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb_dp usb_dp input voltage C0.3 3.63 v v usb_dm usb_dm input voltage C0.3 3.63 v v regin usb regulator input C0.3 6.0 v 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 1. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. ? c l =30 pf loads ? slew rate disabled ? normal drive strength general 6 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 5. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio io pin negative dc injection current single pin ? v in < v ss -0.3v -3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents of 16 contiguous pins ? negative current injection -25 ma v odpu open drain pullup voltage level v dd v dd v 2 v ram v dd voltage required to retain ram 1.2 v 1. all i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v io_min (= v ss -0.3 v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r = (v io_min - v in )/|i icio |. 2. open drain outputs must be pulled to v dd . 2.2.2 lvd and por operating requirements table 6. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v table continues on the next page... general kinetis kl27 microcontroller, rev.5, 08/2015. 7 freescale semiconductor, inc. table 6. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvdh falling low-voltage detect threshold high range (lvdv = 01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv = 00) ? level 2 falling (lvwv = 01) ? level 3 falling (lvwv = 10) ? level 4 falling (lvwv = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv = 00) ? level 2 falling (lvwv = 01) ? level 3 falling (lvwv = 10) ? level 4 falling (lvwv = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage 2.2.3 voltage and current operating behaviors table 7. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage normal drive pad ? 2.7 v v dd 3.6 v, i oh = C5 ma ? 1.71 v v dd 2.7 v, i oh = C1.5 ma v dd C 0.5 v dd C 0.5 v v 1 v oh output high voltage high drive pad ? 2.7 v v dd 3.6 v, i oh = C18 ma ? 1.71 v v dd 2.7 v, i oh = C6 ma v dd C 0.5 v dd C 0.5 v v 1 i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad 0.5 v 1 table continues on the next page... general 8 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 7. voltage and current operating behaviors (continued) symbol description min. max. unit notes ? 2.7 v v dd 3.6 v, i ol = 5 ma ? 1.71 v v dd 2.7 v, i ol = 1.5 ma 0.5 v v ol output low voltage high drive pad ? 2.7 v v dd 3.6 v, i ol = 18 ma ? 1.71 v v dd 2.7 v, i ol = 6 ma 0.5 0.5 v v 1 i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 a 2 i in input leakage current (per pin) at 25 c 0.025 a 2 i in input leakage current (total all pins) for full temperature range 64 a 2 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 3 1. ptb0, ptb1, ptc3, ptc4, ptd6, and ptd7 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. measured at v dd = 3.6 v 3. measured at v dd supply voltage = v dd min and vinput = v ss 2.2.4 power mode transition operating behaviors all specifications except t por and vllsxrun recovery times in the following table assume this clock configuration: ? cpu and system clocks = 48 mhz ? bus and flash clock = 24 mhz ? hirc clock mode table 8. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls0 run 152 166 s ? vlls1 run 152 166 s ? vlls3 run 93 104 s table continues on the next page... general kinetis kl27 microcontroller, rev.5, 08/2015. 9 freescale semiconductor, inc. table 8. power mode transition operating behaviors (continued) symbol description min. typ. max. unit notes ? lls run 7.5 8 s ? vlps run 7.5 8 s ? stop run 7.5 8 s 1. normal boot (ftfa_fopt[lpboot]=11) 2.2.5 power consumption operating behaviors the maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). note the while (1) test is executed with flash cache enabled. table 9. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_runco running coremark in flash in compute operation mode48m hirc mode, 48 mhz core / 24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 5.76 6.04 6.40 6.68 ma 2 i dd_runco running while(1) loop in flash in compute operation mode48m hirc mode, 48 mhz core / 24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 3.21 3.49 3.85 4.13 ma i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 6.45 6.75 7.09 7.39 ma 2 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable, 24 mhz core/12 mhz flash, v dd = 3.0 v 3.95 4.23 4.59 4.87 ma 2 table continues on the next page... general 10 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? at 25 c ? at 105 c i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable 12 mhz core/6 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 2.68 2.96 3.32 3.60 ma 2 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock enable 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 8.08 8.39 8.72 9.03 ma 2 i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 3.90 4.21 4.54 4.85 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 24 mhz core/12 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 2.66 2.94 3.30 3.58 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 12 mhz core/6 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 2.03 2.31 2.67 2.95 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock enable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 5.52 5.83 6.16 6.47 ma i dd_run run mode current48m hirc mode, running while(1) loop in sram all peripheral clock disable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 5.29 5.56 5.93 6.20 ma i dd_run run mode current48m hirc mode, running while(1) loop in sram all peripheral clock enable, 48 mhz core/24 mhz flash, v dd = 3.0 v 6.91 7.19 7.55 7.91 ma table continues on the next page... general kinetis kl27 microcontroller, rev.5, 08/2015. 11 freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? at 25 c ? at 105 c i dd_vlprco very low power run core mark in flash in compute operation mode: core@4mhz, flash @1mhz, v dd = 3.0 v ? at 25 c 826 907 a i dd_vlprco very-low-power-run while(1) loop in sram in compute operation mode 8 mhz lirc mode, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 405 486 a i dd_vlprco very-low-power run while(1) loop in sram in compute operation mode:2 mhz lirc mode, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 154 235 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 108 189 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 125 khz core / 31.25 khz flash, v dd = 3.0 v ? at 25 c 39 120 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 249 330 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in flash all peripheral clock enable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 337 418 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in sram in all peripheral clock disable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 416 497 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in sram all peripheral clock enable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 494 575 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram in all peripheral clock disable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 166 247 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram all peripheral clock table continues on the next page... general 12 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes disable, 125 khz core / 31.25 khz flash, v dd = 3.0 v ? at 25 c 50 131 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram all peripheral clock enable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 208 289 a i dd_wait wait mode currentcore disabled, 48 mhz system/24 mhz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, mcg_lite under hirc mode, v dd = 3.0 v 1.81 1.89 ma i dd_wait wait mode currentcore disabled, 24 mhz system/12 mhz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, mcg_lite under hirc mode, v dd = 3.0 v 1.22 1.39 ma i dd_vlpw very-low-power wait mode current, core disabled, 4 mhz system/ 1 mhz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 172 182 a i dd_vlpw very-low-power wait mode current, core disabled, 2 mhz system/ 0.5 mhz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 69 76 a i dd_vlpw very-low-power wait mode current, core disabled, 125 khz system/ 31.25 khz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 36 40 a i dd_pstop2 partial stop 2, core and system clock disabled, 12 mhz bus and flash, v dd = 3.0 v 1.81 2.06 ma i dd_pstop2 partial stop 2, core and system clock disabled, flash doze enabled, 12 mhz bus, v dd = 3.0 v 1.00 1.25 ma i dd_stop stop mode current at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 161.93 181.45 236.29 390.33 171.82 191.96 271.17 465.58 a i dd_vlps very-low-power stop mode current at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 3.31 10.43 34.14 104.38 5.14 17.68 61.06 164.44 a i dd_vlps very-low-power stop mode current at 1.8 v ? at 25 c and below 3.21 5.22 table continues on the next page... general kinetis kl27 microcontroller, rev.5, 08/2015. 13 freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? at 50 c ? at 85 c ? at 105 c 10.26 33.49 102.92 17.62 60.19 162.20 a i dd_lls low-leakage stop mode current, all peripheral disable, at 3.0 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 2.06 4.72 8.13 13.34 41.08 3.33 6.85 13.30 24.70 52.43 a i dd_lls low-leakage stop mode current with rtc current, at 3.0 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 2.46 5.12 8.53 13.74 41.48 3.73 7.25 11.78 18.91 52.83 a i dd_lls low-leakage stop mode current with rtc current, at 1.8 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 2.35 4.91 8.32 13.44 40.47 2.70 6.75 11.78 18.21 51.85 a 3 i dd_vlls3 very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 1.45 3.37 5.76 9.72 30.41 1.85 4.39 8.48 14.30 37.50 a i dd_vlls3 very-low-leakage stop mode 3 current with rtc current, at 3.0 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 2.05 3.97 6.36 10.32 31.01 2.45 4.99 9.08 14.73 38.10 a 3 table continues on the next page... general 14 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 9. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlls3 very-low-leakage stop mode 3 current with rtc current, at 1.8 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 1.96 3.86 6.23 10.21 30.25 2.36 5.67 8.53 13.37 37.02 a 3 i dd_vlls1 very-low-leakage stop mode 1 current all peripheral disabled at 3.0 v ? at 25 c and below ? at 50c ? at 70c ? at 85c ? at 105 c 0.66 1.78 2.55 4.83 16.42 0.80 3.87 4.26 6.64 20.49 a i dd_vlls1 very-low-leakage stop mode 1 current rtc enabled at 3.0 v ? at 25 c and below ? at 50c ? at 70c ? at 85c ? at 105 c 1.26 2.38 3.15 5.43 17.02 1.40 4.47 4.86 7.24 21.09 a 3 i dd_vlls1 very-low-leakage stop mode 1 current rtc enabled at 1.8 v ? at 25 c and below ? at 50c ? at 70c ? at 85c ? at 105 c 1.16 1.96 2.78 4.85 15.78 1.30 2.28 3.37 6.88 18.81 a 3 i dd_vlls0 very-low-leakage stop mode 0 current all peripheral disabled (smc_stopctrl[porpo] = 0) at 3.0 v ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 0.35 1.25 2.53 4.40 16.09 0.47 1.44 3.24 5.24 19.29 a i dd_vlls0 very-low-leakage stop mode 0 current all peripheral disabled (smc_stopctrl[porpo] = 1) at 3 v general kinetis kl27 microcontroller, rev.5, 08/2015. 15 freescale semiconductor, inc. table 9. power consumption operating behaviors symbol description min. typ. max. unit notes ? at 25 c and below ? at 50 c ? at 70 c ? at 85 c ? at 105 c 0.18 1.09 2.25 4.25 15.95 0.28 1.31 2.94 5.10 19.10 a 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. mcg_lite configured for hirc mode. coremark benchmark compiled using iar 7.10 with optimization level high, optimized for balanced. 3. rtc uses external 32 khz crystal as clock source, and the current includes erclk32k power consumption. table 10. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irc8mhz 8 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 8 mhz irc enabled, mcg_sc[fcrdiv]=000b, mcg_mc[lirc_div2]=000b. 93 93 93 93 93 93 a i irc2mhz 2 mhz internal reference clock (irc) adder. measured by entering stop mode with the 2 mhz irc enabled, mcg_sc[fcrdiv]=000b, mcg_mc[lirc_div2]=000b. 29 29 29 29 29 29 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 224 230 238 245 253 a i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. ? vlls1 ? vlls3 ? lls ? vlps ? stop 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 na i lptmr lptmr peripheral adder measured by placing the device in vlls1 mode with lptmr enabled using lpo. 30 30 30 85 100 200 table continues on the next page... general 16 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 10. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 na i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. ? irc8m (8 mhz internal reference clock) ? irc2m (2 mhz internal reference clock) 114 34 114 34 114 34 114 34 114 34 114 34 a i tpm tpm peripheral adder measured by placing the device in stop or vlps mode with selected clock source configured for output compare generating 100 hz clock signal. no load is placed on the i/o generating the clock signal. includes selected clock source and i/o switching currents. ? irc8m (8 mhz internal reference clock) ? irc2m (2 mhz internal reference clock) 147 42 147 42 147 42 147 42 147 42 147 42 a i bg bandgap adder when bgen bit is set and device is placed in vlpx or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 330 330 330 330 330 330 a 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg-lite in hirc for run mode, and lirc for vlpr mode ? usb regulator disabled ? no gpios toggled ? code execution from flash ? for the alloff curve, all peripheral clocks are disabled except ftfa general kinetis kl27 microcontroller, rev.5, 08/2015. 17 freescale semiconductor, inc. figure 2. run mode supply current vs. core frequency general 18 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. general kinetis kl27 microcontroller, rev.5, 08/2015. 19 freescale semiconductor, inc. current consumption on vdd (a) current consumption on vdd (a) figure 3. vlpr mode current vs. core frequency 2.2.6 emc radiated emissions operating behaviors table 11. emc radiated emissions operating behaviors for 64-pin lqfp package symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 11 dbv 1, 2 v re2 radiated emissions voltage, band 2 50C150 12 dbv v re3 radiated emissions voltage, band 3 150C500 10 dbv v re4 radiated emissions voltage, band 4 500C1000 6 dbv v re_iec iec level 0.15C1000 n 2, 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement general 20 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method. measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = irc48m, f sys = 48 mhz, f bus = 24 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com. 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 12. capacitance attributes symbol description min. max. unit c in input capacitance 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 13. device clock specifications symbol description min. max. unit normal run mode f sys system and core clock 1 48 mhz f bus bus clock 1 24 mhz f flash flash clock 1 24 mhz f sys_usb system and core clock when full speed usb in operation 20 mhz f lptmr lptmr clock 24 mhz vlpr and vlps modes 2 f sys system and core clock 4 mhz f bus bus clock 1 mhz f flash flash clock 1 mhz table continues on the next page... general kinetis kl27 microcontroller, rev.5, 08/2015. 21 freescale semiconductor, inc. table 13. device clock specifications (continued) symbol description min. max. unit f lptmr lptmr clock 3 24 mhz f lptmr_erclk lptmr external reference clock 16 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 16 mhz f tpm tpm asynchronous clock 8 mhz f lpuart0/1 lpuart0/1 asynchronous clock 8 mhz 1. the maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher than the specified maximum frequency when irc 48mhz is used as the clock source. 2. the frequency limitations in vlpr and vlps modes here override any frequency specification listed in the timing specification for any other module. these same frequency limits apply to vlps, whether vlps was entered from run or from vlpr. 3. the lptmr can be clocked at this speed in vlpr or vlps only when the source is an external pin. 2.3.2 general switching specifications these general-purpose specifications apply to all signals configured for gpio and uart signals. table 14. general switching specifications description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 16 ns 2 port rise and fall time 36 ns 3 1. the synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 75 pf load 2.4 thermal specifications general 22 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 2.4.1 thermal operating requirements table 15. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed the maximum. the simplest method to determine t j is: t j = t a + r ja chip power dissipation. 2.4.2 thermal attributes table 16. thermal attributes board type symbol description 48 qfn 32 qfn 64 lqfp 64 mapbg a unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 86 101 70 50.3 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 29 33 51 42.9 c/w single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 71 84 58 41.4 c/w four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 24 28 45 38.0 c/w r jb thermal resistance, junction to board 12 13 33 39.6 c/w 2 r jc thermal resistance, junction to case 1.7 1.7 20 27.3 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 3 4 0.4 c/w 4 jb thermal characterization parameter, junction to package bottom (natural convection) - - - 12.6 c/w 5 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air), or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air). 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board. 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits, with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. general kinetis kl27 microcontroller, rev.5, 08/2015. 23 freescale semiconductor, inc. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air). 5. thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per jedec jesd51-12. when greek letters are not available, the thermal characterization parameter is written as psi-jb. 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 swd electricals table 17. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 swd_clk frequency of operation ? serial wire debug 0 25 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 4. serial wire clock input timing peripheral operating requirements and behaviors 24 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 5. serial wire data timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules 3.3.1 mcg-lite specifications table 18. irc48m specification symbol description min. typ. max. unit notes i dd supply current 400 500 a f irc output frequency 48 mhz f irc48m_ol_lv open loop total deviation of irc48m frequency at low voltage (vdd=1.71v-1.89v) over temperature 0.5 1.5 %f irc48m 1 f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over temperature 0.5 1.0 %f irc48m 1 table continues on the next page... peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 25 freescale semiconductor, inc. table 18. irc48m specification (continued) symbol description min. typ. max. unit notes t j period jitter (rms) 35 150 ps t su startup time 2 3 s 1. the maximum value represents characterized results equivalent to mean plus or minus three times the standard deviation (mean +/-3sigma). table 19. irc8m/2m specification symbol description min. typ. max. unit notes i dd_2m supply current in 2 mhz mode 14 17 a i dd_8m supply current in 8 mhz mode 30 35 a f irc_2m output frequency 2 mhz f irc_8m output frequency 8 mhz f irc_t_2m output frequency range (trimmed) 3 %f irc f irc_t_8m output frequency range (trimmed) 3 %f irc t su_2m startup time 12.5 s t su_8m startup time 12.5 s peripheral operating requirements and behaviors 26 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. figure 6. irc8m frequency drift vs temperature curve 3.3.2 oscillator electrical specifications 3.3.2.1 oscillator dc electrical specifications table 20. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz 500 200 300 950 1.2 na a a a ma 1 table continues on the next page... peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 27 freescale semiconductor, inc. table 20. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes ? 24 mhz ? 32 mhz 1.5 ma i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2, 3 c y xtal load capacitance 2, 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2, 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low- power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation peripheral operating requirements and behaviors 28 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 3. c x ,c y can be provided by using the integrated capacitors when the low frequency oscillator (range = 00) is used. for all other cases external capacitors must be used. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 oscillator frequency specifications table 21. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high-frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 48 mhz 1, 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3, 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 3.4 memories and memory interfaces 3.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 29 freescale semiconductor, inc. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 22. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk128k erase block high-voltage time for 128 kb 52 452 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 23. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk128k read 1s block execution time ? 128 kb program flash 1.7 ms 1 t rd1sec1k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersblk128k erase flash block execution time ? 128 kb program flash 88 600 ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 1.8 ms 1 t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 175 1300 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t ersallu erase all blocks unsecure execution time 175 1300 ms 2 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. peripheral operating requirements and behaviors 30 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 3.4.1.3 flash high voltage current behaviors table 24. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.4.1.4 reliability specifications table 25. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at C40 c t j 125 c. 3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog 3.6.1 adc electrical specifications using differential inputs can achieve better system accuracy than using single-end inputs. peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 31 freescale semiconductor, inc. 3.6.1.1 16-bit adc operating conditions table 26. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v 3 v refl adc reference voltage low v ssa v ssa v ssa v 3 v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 4 f adck adc conversion clock frequency 13-bit mode 1.0 24 mhz 5 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 5 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 1200 ksps 6 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 6 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. vrefh can act as vref_out when vrefv1 module is enabled. 4. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 5. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 6. for guidelines and examples of conversion rate calculation, download the adc calculator tool. peripheral operating requirements and behaviors 32 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. r as v as cas zas vadin z adin r adin radin radin radin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 7. adc input impedance equivalency diagram 3.6.1.2 16-bit adc electrical characteristics table 27. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes 1.0 C2.7 to +1.9 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 33 freescale semiconductor, inc. table 27. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? <12-bit modes 0.5 C0.7 to +0.5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda peripheral operating requirements and behaviors 34 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 8. typical enob vs. adc_clk for 16-bit differential mode typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 12 11 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 9. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 35 freescale semiconductor, inc. 3.6.2 voltage reference electrical specifications table 28. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1, 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. table 29 is tested under the condition of setting vref_trm[chopen], vref_sc[regen] and vref_sc[icompen] bits to 1. table 29. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v 1 v out voltage reference output factory trim 1.1584 1.2376 v 1 v out voltage reference output user trim 1.193 1.197 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range: 0 to 70c) 50 mv 1 i bg bandgap only current 80 a 1 i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = 1.0 ma 200 v 1, 2 t stup buffer startup time 100 s t chop_osc_st up internal bandgap start-up delay with chop oscillator enabled 35 ms v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load peripheral operating requirements and behaviors 36 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 30. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 31. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 3.6.3 cmp and 6-bit dac electrical specifications table 32. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 37 freescale semiconductor, inc. 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.8 2.5 2.2 1.9 1.6 1.3 1 0.7 0.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 10. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors 38 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 11. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.6.4 12-bit dac electrical characteristics 3.6.4.1 12-bit dac operating requirements table 33. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 39 freescale semiconductor, inc. 3.6.4.2 12-bit dac operating behaviors table 34. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 250 a i dda_dach p supply current high-speed mode 900 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device peripheral operating requirements and behaviors 40 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 12. typical inl error vs. digital code peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 41 freescale semiconductor, inc. temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 13. offset at half scale vs. temperature 3.7 timers see general switching specifications. 3.8 communication interfaces 3.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit usb.org . peripheral operating requirements and behaviors 42 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. note the irc48m do not meet the usb jitter specifications for certification for host mode operation. this device cannot support host mode operation. 3.8.2 usb vreg electrical specifications table 35. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 125 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 10 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25 c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 43 freescale semiconductor, inc. 3.8.3 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pf maximum load on all spi pins. table 36. spi master mode timing on slew rate disabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 18 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 15 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph table 37. spi master mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 96 ns 7 t hi data hold time (inputs) 0 ns table continues on the next page... peripheral operating requirements and behaviors 44 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 37. spi master mode timing on slew rate enabled pads (continued) num. symbol description min. max. unit note 8 t v data valid (after spsck edge) 52 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 14. spi master mode timing (cpha = 0) peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 45 freescale semiconductor, inc. < table 39. spi slave mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation 0 f periph /4 hz 1 2 t spsck spsck period 4 x t periph ns 2 3 t lead enable lead time 1 t periph 4 t lag enable lag time 1 t periph 5 t wspsck clock (spsck) high or low time t periph - 30 ns 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 122 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). for spi1 f periph is the system clock (f sys ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 16. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 47 freescale semiconductor, inc. 2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 17. spi slave mode timing (cpha = 1) 3.8.4 i 2 c 3.8.4.1 inter-integrated circuit interface (i2c) timing table 40. i2c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 1 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 2 3.45 3 0 4 0.9 2 s data set-up time t su ; dat 250 5 100 3 , 6 ns rise time of sda and scl signals t r 1000 20 +0.1c b 7 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 6 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns peripheral operating requirements and behaviors 48 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 1. the maximum scl clock frequency in fast mode with maximum bus loading can be achieved only when using the high drive pins across the full voltage range and when using the normal drive pins and vdd 2.7 v. 2. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 3. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 4. input signal slew = 10 ns and output load = 50 pf 5. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 6. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 7. c b = total capacitance of the one bus line in pf. to achieve 1mhz i2c clock rates, consider the following recommendations: ? to counter the effects of clock stretching, the i2c baud rate select bits can be configured for faster than desired baud rate. ? use high drive pad and dse bit should be set in portx_pcrn register. ? minimize loading on the i2c sda and scl pins to ensure fastest rise times for the scl line to avoid clock stretching. ? use smaller pull up resistors on sda and scl to reduce the rc time constant. table 41. i 2 c 1mbit/s timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 s low period of the scl clock t low 0.5 s high period of the scl clock t high 0.26 s set-up time for a repeated start condition t su ; sta 0.26 s data hold time for i 2 c bus devices t hd ; dat 0 s data set-up time t su ; dat 50 ns rise time of sda and scl signals t r 20 +0.1c b 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns set-up time for stop condition t su ; sto 0.26 s bus free time between stop and start condition t buf 0.5 s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns 1. the maximum scl clock frequency of 1 mbit/s can support maximum bus loading when using the high drive pins across the full voltage range. 2. c b = total capacitance of the one bus line in pf. peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 49 freescale semiconductor, inc. ? ? figure 18. timing definition for devices on the i 2 c bus 3.8.5 uart see general switching specifications. 3.8.6 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 3.8.6.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 42. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15.5 ns table continues on the next page... peripheral operating requirements and behaviors 50 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 42. i2s/sai master mode timing (continued) num. characteristic min. max. unit s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 19 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 26 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 19. i2s/sai timing master modes table 43. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 10 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 33 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 10 ns table continues on the next page... peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 51 freescale semiconductor, inc. table 43. i2s/sai slave mode timing (continued) num. characteristic min. max. unit s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 28 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 20. i2s/sai timing slave modes 3.8.6.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 44. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns table continues on the next page... peripheral operating requirements and behaviors 52 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. table 44. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 21. i2s/sai timing master modes table 45. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 87 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns peripheral operating requirements and behaviors kinetis kl27 microcontroller, rev.5, 08/2015. 53 freescale semiconductor, inc. 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 22. i2s/sai timing slave modes 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 32-pin qfn 98asa00615d 48-pin qfn 98asa00616d 64-pin lqfp 98ass23234w 64-pin mapbga 98asa00420d dimensions 54 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. pinouts and packaging 5.1 kl27 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. note vrefh can act as vref_out when vrefv1 module is enabled. note it is prohibited to set vrefen in 32 qfn pin package as 1.2 v on-chip voltage is not available in this package. 32 qfn 48 qfn 64 map bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 b1 2 pte1 disabled pte1 spi1_mosi lpuart1_ rx spi1_miso i2c1_scl 1 3 vdd vdd vdd 7 g1 9 pte20 adc0_dp0/ adc0_se0 adc0_dp0/ adc0_se0 pte20 tpm1_ch0 lpuart0_ tx fxi00_d4 8 f1 10 pte21 adc0_dm0/ adc0_se4a adc0_dm0/ adc0_se4a pte21 tpm1_ch1 lpuart0_ rx fxio0_d5 g2 11 pte22 adc0_dp3/ adc0_se3 adc0_dp3/ adc0_se3 pte22 tpm2_ch0 uart2_tx fxio0_d6 f2 12 pte23 adc0_dm3/ adc0_se7a adc0_dm3/ adc0_se7a pte23 tpm2_ch1 uart2_rx fxio0_d7 10 g4 14 vrefh vrefh vrefh 11 g3 15 vrefl vrefl vrefl 13 h1 17 pte29 cmp0_in5/ adc0_se4b cmp0_in5/ adc0_se4b pte29 tpm0_ch2 tpm_ clkin0 h3 19 pte31 disabled pte31 tpm0_ch4 15 h4 20 pte24 disabled pte24 tpm0_ch0 i2c0_scl 16 h5 21 pte25 disabled pte25 tpm0_ch1 i2c0_sda f5 27 pta5 disabled pta5 usb_clkin tpm0_ch2 i2s0_tx_ bclk h6 28 pta12 disabled pta12 tpm1_ch0 i2s0_txd0 g6 29 pta13 disabled pta13 tpm1_ch1 i2s0_tx_fs 29 e7 37 ptb2 adc0_se12 adc0_se12 ptb2 i2c0_scl tpm2_ch0 30 e8 38 ptb3 adc0_se13 adc0_se13 ptb3 i2c0_sda tpm2_ch1 5 pinouts and packaging kinetis kl27 microcontroller, rev.5, 08/2015. 55 freescale semiconductor, inc. 32 qfn 48 qfn 64 map bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 31 e6 39 ptb16 disabled ptb16 spi1_mosi lpuart0_ rx tpm_ clkin0 spi1_miso 32 d7 40 ptb17 disabled ptb17 spi1_miso lpuart0_ tx tpm_ clkin1 spi1_mosi d6 41 ptb18 disabled ptb18 tpm2_ch0 i2s0_tx_ bclk c7 42 ptb19 disabled ptb19 tpm2_ch1 i2s0_tx_fs 33 d8 43 ptc0 adc0_se14 adc0_se14 ptc0 extrg_in audiousb_ sof_out cmp0_out i2s0_txd0 e3 47 vss vss vss e4 48 vdd vdd vdd a6 53 ptc8 cmp0_in2 cmp0_in2 ptc8 i2c0_scl tpm0_ch4 i2s0_mclk b5 54 ptc9 cmp0_in3 cmp0_in3 ptc9 i2c0_sda tpm0_ch5 i2s0_rx_ bclk b4 55 ptc10 disabled ptc10 i2c1_scl i2s0_rx_fs a5 56 ptc11 disabled ptc11 i2c1_sda i2s0_rxd0 41 c3 57 ptd0 disabled ptd0 spi0_ss tpm0_ch0 fxi00_d0 42 a4 58 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck tpm0_ch1 fxio0_d1 43 c2 59 ptd2 disabled ptd2 spi0_mosi uart2_rx tpm0_ch2 spi0_miso fxio0_d2 44 b3 60 ptd3 disabled ptd3 spi0_miso uart2_tx tpm0_ch3 spi0_mosi fxio0_d3 c5 nc nc nc 1 a1 1 pte0 disabled pte0/ clkout32k spi1_miso lpuart1_ tx rtc_ clkout cmp0_out i2c1_sda 2 2 c4 4 vss vss vss 3 3 e1 5 usb0_dp usb0_dp usb0_dp 4 4 d1 6 usb0_dm usb0_dm usb0_dm 5 5 e2 7 vout33 vout33 vout33 6 6 d2 8 vregin vregin vregin 7 9 f4 13 vdda vdda vdda 8 12 f3 16 vssa vssa vssa 9 14 h2 18 pte30 dac0_out/ adc0_se23/ cmp0_in4 dac0_out/ adc0_se23/ cmp0_in4 pte30 tpm0_ch3 tpm_ clkin1 lpuart1_ tx lptmr0_ alt1 10 17 d3 22 pta0 swd_clk pta0 tpm0_ch5 swd_clk 11 18 d4 23 pta1 disabled pta1 lpuart0_ rx tpm2_ch0 12 19 e5 24 pta2 disabled pta2 lpuart0_ tx tpm2_ch1 13 20 d5 25 pta3 swd_dio pta3 i2c1_scl tpm0_ch0 swd_dio 14 21 g5 26 pta4 nmi_b pta4 i2c1_sda tpm0_ch1 nmi_b 15 22 g7 30 vdd vdd vdd 16 23 h7 31 vss vss vss pinouts and packaging 56 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 32 qfn 48 qfn 64 map bga 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 17 24 h8 32 pta18 extal0 extal0 pta18 lpuart1_ rx tpm_ clkin0 18 25 g8 33 pta19 xtal0 xtal0 pta19 lpuart1_ tx tpm_ clkin1 lptmr0_ alt1 19 26 f8 34 pta20 reset_b pta20 reset_b 20 27 f7 35 ptb0/ llwu_p5 adc0_se8 adc0_se8 ptb0/ llwu_p5 i2c0_scl tpm1_ch0 21 28 f6 36 ptb1 adc0_se9 adc0_se9 ptb1 i2c0_sda tpm1_ch1 22 34 c6 44 ptc1/ llwu_p6/ rtc_clkin adc0_se15 adc0_se15 ptc1/ llwu_p6/ rtc_clkin i2c1_scl tpm0_ch0 i2s0_txd0 23 35 b7 45 ptc2 adc0_se11 adc0_se11 ptc2 i2c1_sda tpm0_ch1 i2s0_tx_fs 24 36 c8 46 ptc3/ llwu_p7 disabled ptc3/ llwu_p7 spi1_sck lpuart1_ rx tpm0_ch2 clkout i2s0_tx_ bclk 25 37 b8 49 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_ss lpuart1_ tx tpm0_ch3 i2s0_mclk 26 38 a8 50 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 cmp0_out 27 39 a7 51 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_mosi extrg_in i2s0_rx_ bclk spi0_miso i2s0_mclk 28 40 b6 52 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_miso audiousb_ sof_out i2s0_rx_fs spi0_mosi 29 45 a3 61 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi1_ss uart2_rx tpm0_ch4 fxi00_d4 30 46 c1 62 ptd5 adc0_se6b adc0_se6b ptd5 spi1_sck uart2_tx tpm0_ch5 fxio0_d5 31 47 b2 63 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi1_mosi lpuart0_ rx spi1_miso fxio0_d6 32 48 a2 64 ptd7 disabled ptd7 spi1_miso lpuart0_ tx spi1_mosi fxio0_d7 5.2 kl27 family pinouts figure below shows the 32 qfn pinouts: pinouts and packaging kinetis kl27 microcontroller, rev.5, 08/2015. 57 freescale semiconductor, inc. 32 31 30 29 28 27 26 25 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 pta2 pta1 pta0 pte30 12 11 10 9 vss vdd pta4 pta3 16 15 14 13 ptb0/llwu_p5 pta20 pta19 pta18 24 23 22 21 20 19 18 17 ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptb1 vssa vdda vregin vout33 usb0_dm usb0_dp vss pte0 8 7 6 5 4 3 2 1 figure 23. 32 qfn pinout diagram figure below shows the 48 qfn pinouts: pinouts and packaging 58 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. vssa vrefl vrefh vdda pte21 pte20 vregin vout33 usb0_dm usb0_dp vss vdd 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2 ptd1 ptd0 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 36 35 34 33 ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptc0 32 31 30 29 28 27 26 25 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta3 pta2 pta1 pta0 24 23 22 21 20 19 18 17 pte25 pte24 pte30 pte29 16 15 14 13 pta18 vss vdd pta4 figure 24. 48 qfn pinout diagram figure below shows the 64 lqfp pinouts: pinouts and packaging kinetis kl27 microcontroller, rev.5, 08/2015. 59 freescale semiconductor, inc. pte24 pte31 pte30 pte29 vssa vrefl vrefh vdda pte23 pte22 pte21 pte20 vregin vout33 usb0_dm usb0_dp vss vdd pte1 pte0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2 ptd1 ptd0 ptc11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6/rtc_clkin ptc0 ptb19 ptb18 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta18 vss vdd pta13 pta12 pta5 pta4 pta3 pta2 pta1 pta0 pte25 figure 25. 64 lqfp pinout diagram figure below shows the 64 mapbga pinouts: pinouts and packaging 60 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 1 a pte0 b pte1 c ptd5 d usb0_dm e usb0_dp f pte21 g pte20 1 h pte29 2 ptd7 ptd6/ llwu_p1 5 ptd2 vregin vout33 pte23 pte22 2 pte30 3 ptd4/ llwu_p1 4 ptd3 ptd0 pta0 vss vssa vrefl 3 pte31 4 ptd1 ptc10 vss pta1 vdd vdda vrefh 4 pte24 5 ptc11 ptc9 nc pta3 pta2 pta5 pta4 5 pte25 6 ptc8 ptc7 ptc1/ llwu_p6/ r tc_clkin ptb18 ptb16 ptb1 pta13 6 pta12 7 ptc6/ llwu_p1 0 ptc2 ptb19 ptb17 ptb2 ptb0/ llwu_p5 vdd 7 vss 8 a ptc5/ llwu_p9 b ptc4/ llwu_p8 c ptc3/ llwu_p7 d ptc0 e ptb3 f pta20 g pta19 8 h pta18 figure 26. 64 mapbga pinout diagram 6 ordering parts 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: 7 part identification ordering parts kinetis kl27 microcontroller, rev.5, 08/2015. 61 freescale semiconductor, inc. 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q kl## a fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): table 46. part number fields descriptions field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kl## kinetis family ? kl27 a key attribute ? z = cortex-m0+ fff program flash memory size r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) cc maximum cpu frequency (mhz) ? 4 = 48 mhz n packaging type ? r = tape and reel 7.4 example this is an example part number: mkl27z256vft4 part identification 62 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 8 terminology and guidelines 8.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. terminology and guidelines kinetis kl27 microcontroller, rev.5, 08/2015. 63 freescale semiconductor, inc. 8.2 examples operating rating: operating requirement: operating behavior that includes a typical value: example example example example 8.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v terminology and guidelines 64 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. 8.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9 revision history the following table provides a revision history for this document. table 47. revision history rev. no. date substantial changes 3 09 august 2014 initial public release ? updated table 9 - power consumption operating behaviors. ? added a note related to 32 qfn pin package in pinouts topic. 4 03 march 2015 ? updated the features and completed the ordering information. ? removed thickness dimension from package diagrams. table continues on the next page... revision history kinetis kl27 microcontroller, rev.5, 08/2015. 65 freescale semiconductor, inc. table 47. revision history (continued) rev. no. date substantial changes ? updated related resources table to include chip errata resource name and package drawing part numbers in the respective rows. also updated product brief resource references. ? updated table 7. voltage and current operating behaviors. ? specified correct max. value for i in . ? updated table - 9 power consumption operating behaviors. ? rows added for idd for reset pin hold low (i dd_reset_low ) at 1.7v and 3v. ? measurement unit updated for i dd_vlls1 from na to a. ? footnote 1 was moved in the beginning of the table as text. ? added table - 11 emc radiated emissions operating behaviors for 64-pin lqfp package under section 2.2.6. ? updated table - 18 (irc48m specification) and table - 19 (irc8m/2m specification) under section 3.3.1 - 'mcg-lite specifications'. ? removed supply voltage (v dd ), temperature range (t), untrimmed (f irc_ut ), trim function (f irc_c , f irc_f ) data from table - 18 (irc48m specification). ? removed supply voltage (v dd ), temperature range (t) data from table - 19 (irc8m/2m specification). ? added figure 6. irc8m frequency drift vs temperature curve after table - 19 (irc8m/2m specification). ? updated table 29. vref full-range operating behaviors. ? removed a c (aging coefficient) row. ? added t chop_osc_stup parameter. ? added tables: "i2c timing" and "i2c 1mbit/s timing" under section - i 2 c. ? added vref specifications (v refh and v refl ) to table 26. 16-bit adc operating conditions. ? removed note: this device does not have the usb_clkin signal available. 5 12 august 2015 ? in table 9. power consumption operating behaviors: ? updated max. values of i dd_wait , i dd_vlpw , i dd_stop , i dd_vlps , i dd_lls , i dd_vlls3 , i dd_vlls1 , i dd_vlls0 . ? modified unit of i dd_vlls0 from na to a. ? removed i dd_reset_low information. ? in table 13. device clock specifications, added a footnote for normal run mode. ? in table 15. thermal operating requirements, modified the footnote for ambient temperature. ? in table 18. irc48m specification, removed f irc_t data and added f irc48m_of_lv and f irc48m_of_hv specifications. ? in table 26. 16-bit adc operating conditions, updated max. value of f adck and c rate . revision history 66 kinetis kl27 microcontroller, rev.5, 08/2015. freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. freescale, the freescale logo, energy efficient solutions logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ?2014-2015 freescale semiconductor, inc. document number KL27P64M48SF6 revision 5, 08/2015 |
Price & Availability of KL27P64M48SF6
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |